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TAMC900 8 Channel 105 MSps 14 Bit AD Converter |
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8 Channel
14 Bit AD Converter with Front Panel I/O and FPGA The TAMC900 contains additionally a Virtex-5 FPGA. The FPGA controls the data transfer to the CPU over a PCIe x8 interface and controls 4 MB SRAM, which enables snapshots of all ADCs at full speed and full resolution for 2 ms. AMC Port 4-11 on the TAMC900-10R or Port 0, 1 and 4-9 on the TAMC900-25R can be used to transmit the ADC data to the CPU. A signal Conditioning adapter (SiCA) allows to realize different front I/O solutions for customer requirements. The SiCA TAMC900-A1-10 offers eight differential inputs, three clock and three triggers inputs and a gain of 1. The three external clock inputs and the PCIe reference clock are routed to a flexible clocking scheme that allows independent clocking of the ADCs in two groups. The trigger inputs are routed to the FPGA. The FPGA is configured from an on-board flash. This flash memory and the FPGA can programmed on the JTAG interface. The flash can save two different versions of code. The loaded code version can selected via IPMI. For a In-system update of the FPGA the flash can be programmed via IPMI. A wide range of drivers is available: Windows XP/XPE/2000, Linux, LynxOS, QNX, VxWorks, and Integrity. All drivers - except the Windows drivers - are supplied as C source code.
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