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TCP630 FPGA CPCI Module with 64 TTL or 32 Differential I/Os
TCP630 Block Diagram
TCP630 Block Diagram
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User Configurable FPGA with
600.000 System Gates
The TCP630 is a standard 3U 32 bit CompactPCI module
providing a configurable FPGA with 300.000 or 600.000 system gates. The
TCP630-x0 has 64 TTL lines, the TCP630-x1 provides 32 differential I/O
lines using EIA-422 / EIA-485 compatible
line transceivers. The TCP630-x2 provides 32 TTL and 16 differential
I/Os. All lines are individually programmable as input, output or
tri-state and ESD-protected. The receivers are always enabled, which allows determining
the state of each I/O line at any time. Each TTL I/O line has a pull-up
resistor. The pull-up voltage is selectable to be either +3.3V or +5V.
The differential I/O lines are terminated by 120Ω resistors.
For flexible front I/O solutions the TCP630 has a PIM module slot. The
TPIM0003-10 makes the IO signals available on a HD68. Opt. PIMs with
user specific connectors or additional signal adjustment are possible.
Such a realization is simply, fast and cheap possible. The TCP630-2x
also offer rear I/O via the J2 connector.
The FPGA is configured by a serial Flash. The Flash device is in-system
programmable via driver software over the PCI bus. An in-circuit
debugging option is available via an optionally mountable JTAG header for read back and real-time debugging of
the FPGA design (using Xilinx “ChipScope”). User applications can be
developed using the design software ISE WebPACK which can be downloaded
free of charge from www.xilinx.com.
A wide range of drivers is available: Linux, LynxOS, OS-9, pSOS+, QNX,
VxWorks and Windows. All drivers - except the Windows drivers - are
supplied as C source code.
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Product Specification
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CPCI module, 32 bit/33MHz PCI interface, PCI 2.2 compliant, 3.3V and
5V Vio, 32 bit PCI target interface by PLX PCI9030
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Xilinx XC2S300E-6 Spartan-IIE FPGA configured
by serial Flash XCF02S, Flash device in-system programmable
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FPGA with 300.000 or 600.000 system gates
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FPGA clock options: Local clock oscillator or
PLL programmable clock generator (200 KHz – 166 MHz), 6 clock
outputs connected to FPGA
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I/O lines: 64 TTL I/O (-10), 32 differential
I/O (-11) or 32 TTL I/O and 16 differential I/O (-12), direction
individually programmable
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TTL signaling voltage (maximum current: +/-24 mA) or EIA-422/-485
signaling level
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PIM module slot or J2 I/O
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-40°C .. +85°C operating temperature range
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OS-9, pSOS+, Windows NT/2000/XP, Linux, LynxOS, QNX, and VxWorks drivers available
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5 years warranty
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Ordering Information |
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TCP630-10R |
FPGA cPCI module with 64 TTL I/Os |
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TCP630-11R |
FPGA cPCI module with 32 differential I/Os |
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TCP630-12R |
FPGA cPCI module with 32 TTL and 16 differential I/Os |
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TCP630-20R |
FPGA cPCI module with 64 TTL I/Os, J2 I/O |
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TCP630-21R |
FPGA cPCI module with 32 differential I/Os, J2 I/O |
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TCP630-22R |
FPGA cPCI module with 32 TTL and 16 differential I/Os, J2
I/O |
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TA304-10R
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Cable Kit for modules with HD68 SCSI-3 type connector
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TCP001-FP-10
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6U front panel extension for 3U cPCI boards
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TCP040-TM-10
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Rear I/O transition module with PIM slot
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TPIM003-10R
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PIM I/O module with HD68 SCSI-3 type connector and special pin
assignment
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TDRV004-SW-12
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OS-9 driver
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TDRV004-SW-32
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pSOS, pSOS+ driver
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TDRV004-SW-42
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VxWorks driver
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TDRV004-SW-62
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Windows NT 4.0 driver
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TDRV004-SW-65
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Windows 2000/XP driver
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TDRV004-SW-72
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LynxOS driver
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TDRV004-SW-82
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LINUX driver
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TDRV004-SW-92
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QNX 4 driver
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TDRV004-SW-95
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QNX 6 driver
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TCP630-DOC
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TCP630 Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines User Manual
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TCP630-ED
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Engineering Documentation
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