TQMC600

Reconfigurable FPGA with Digital I/O

QMC module providing a user programmable Xilinx Artix-7 XC7A50T-2 FPGA. Depending on the version, the TQMC600 offers 32 ESD-protected 5V-tolerant TTL lines or 16 differential I/O lines using ESD-protected EIA-422/EIA-485 compatible line transceivers or multipoint LVDS transceivers.

All I/O lines are individually programmable as input or output. The TTL I/O lines can be set to high, low, or tristate. The differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 Ω and M-LVDS lines with 100 Ω. The FPGA is configured by a SPI flash. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design. User applications for the TQMC600 with 7A50T FPGA can be developed using the design software Vivado Design Suite HL WebPACK Edition, which can be downloaded free of charge from www.xilinx.com.

TEWS Technologies offers a well-documented basic FPGA Example Application design. It includes a constraints file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TQMC600. It implements PCIe to register mapping and basic I/O. It comes as a Xilinx Vivado Design Suite project with source code and as a ready-to-download bit stream.

Integrity, VxWorks, QNX, Windows, and Linux drivers are available.