TXMC633

TXMC633 Reconfigurable FPGA with 64 TTL I/O or 32 Diff./M-LVDS I/O

XMC module providing a user configurable Xilinx XC6SLX45T or Xilinx XC6SLX100T FPGA. The TXMC633-x0R has 64 ESD-protected TTL lines, the TXMC633-x1R provides 32 differential I/O lines using EIA-422 / EIA-485 compatible, ESD-protected line transceivers. The TXMC633-x2R provides 32 TTL and 16 differential I/Os, the TXMC633-x3R has 32 M-LVDS I/O lines and the TXMC633-x4R provides 32 TTL I/O and 16 M-LVDS I/O lines. All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either +3.3V or +5V. The differential RS-485 I/O lines are terminated by 120Ω resistors and the differential M-LVDS I/O lines are terminated by 100Ω resistors.

For custom specific I/O extension or inter-board commuication the TXMC633 provides 64 FPGA I/Os on P14 and 3 FPGA Multi-Gigabit transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.

The FPGA is configured by a platform flash SPI flash or via PCIe download. The flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). User applications for the TXMC633 with XC6SLX45T-2 FPGA can be developed using the design software ISE Project Navigator and Embedded Development Kit (EDK).

The TXMC633 provides front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14 and P16.

A wide range of drivers is available: Linux, LynxOS, Integrity, QNX, VxWorks and Windows. All drivers - except the Windows drivers - are supplied as C source code.

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Technical Description

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  • XMC module, 32 bit/33MHz PCI interface, IEEE P1386.1 compliant, PCI 2.2 compliant, 3.3V and 5V Vio
  • Spartan6 FPGA: TXMC633-1x with Xilinx XC6SLX45T-2, TXMC633-2x with Xilinx XC6SLX100T-2
  • Serial Flash
  • 128 MB 16bit DDR3 SDRAM
  • 32 Mbit SPI-EEPROM for FPGA configuration
  • Flash device programmable via JTAG and in-system
  • I/O lines: 64 TTL I/O (-x0R), 32 differential I/O (-x1R), 32 TTL I/O and 16 differential I/O (-x2R), 32 M-LVDS I/O (-x3R) or 32 TTL I/O and 16 M-LVDS I/O (-x4R), direction individually programmable
  • TTL signaling voltage (maximum current: +/-32 mA) or EIA-422/-485 signaling level or M-LVDS standard (EIA-899)
  • Front panel or P14/16 I/O
  • -40°C .. +85°C operating temperature range
  • Integrity, Windows, Linux, LynxOS, QNX, and VxWorks drivers available
  • 5 years warranty

Order Information

TXMC633-10R

XC6SLX45T-2 FPGA XMC module with 64 TTL I/Os

TXMC633-11R

XC6SLX45T-2 FPGA XMC module with 32 differential I/Os

TXMC633-12R

XC6SLX45T-2 FPGA XMC module with 32 TTL and 16 differential I/Os

TXMC633-13R

XC6SLX45T-2 FPGA XMC module with 32 M-LVDS I/Os

TXMC633-14R

XC6SLX45T-2 FPGA XMC module with 32 TTL and 16 M-LVDS I/Os

TXMC633-20R

XC6SLX100T-2 FPGA XMC module with 64 TTL I/Os

TXMC633-21R

XC6SLX100T-2 FPGA XMC module with 32 differential I/Os

TXMC633-22R

XC6SLX100T-2 FPGA XMC module with 32 TTL and 16 differential I/Os

TXMC633-23R

XC6SLX100T-2 FPGA XMC module with 32 M-LVDS I/Os

TXMC633-24R

XC6SLX100T-2 FPGA XMC module with 32 TTL and 16 M-LVDS I/Os

TA104-10R

1.8m cable with HD-68 connectors

TA203-10R

68 pin terminal block with HD-68 connector

TA304-10R

Connection kit 1.8m cable with HD-68 connectors and 68 pin terminal block

TA900-10R

Program and debug box

TPIM003-10R

PIM module with 68 pin SCSI-3 type connector

TDRV018-SW-42

VxWorks driver

TDRV018-SW-82

LINUX driver

TXMC633-FDK

FPGA development kit

Technical Documentation

TXMC633 data sheet

TXMC633 user manual

TA900 data sheet

TA900 user manual

TPIM003 data sheet

TPIM003 user manual

VxWorks driver user manual

LINUX driver user manual