NAMC-SDH

NAMC-SDH AMC Line Interface between SDH/SONET and TDM

Telecommunication interface AMC module, targeting telecom applications dealing with Synchronous Digital Hierarchy (SDH) in SDH/SONET networks. Equipped with an add/drop multiplexer/demultiplexer chipset, the NAMC-SDH is an ideal single board platform to interface between the frame oriented STM-1 or STM-4 SDH/SONET networks and classic TDM E1/T1. The multiplexer/demultiplexer implements 252 E1 or 336 T1 framers as well as four OC-3/STM-1 or two OC-4/STM-4 (one backup) interfaces. The multiplexer/demultiplexer provides also an ESSI link for redundant/fail-over operation which is available at AMC port 16, making it suitable for ATCA based applications.

The on-board Xilinx Kintex-7 FPGA provides the NAMC-SDH with a scalable and flexible but powerful onboard data engine, allowing for pre-processing and/or filtering. The Kintex-7 FPGA also allows the NAMC-SDH to seamlessly interface between the TDM domain and the Ethernet domain as needed by, for example, VoIP applications. The Kintex-7 FPGA is by default equipped with a standard image that implements an iTDM engine and a Time Slot Interchanger (TSI). Two 72 Mbit QDR2+ SRAMs or one 2 GB DDR3 SRAM (default) are connected to the FPGA.

An optional function block for the FPGA implements an HDLC controller, which offers a total capacity of 2000 x 64 kbit/s (2000 x DS0 bandwidth) per direction. It can be configured to handle up to 2000 separate 64 kbit/s channels, or to combine each up to 31 of the 64 kbit/s time-slots to super-channels. The TSI Block is used to either cross-connect a time-slot directly from Rx to Tx, to connect a time-slot to the ITDM controller, or to connect one or multiple of them to a channel of the HDLC controller.

The NAMC-SDH provides four optical interfaces on the front panel (up to four STM-1 or two STM-4 interfaces). The NAMC-SDH offers four 1GbE interfaces at AMC ports 0, 1, 4 and 8. This allows the board to operate in redundant setups as well as to select whether data transfer resides in the AMC Common-Option region (port 0/1) or in the Fat-Pipe region (port 4/8). The NAMC SDH is typically connected for operation in the fat pipe region with a 10G Ethernet switch (e.g., NAT-MCH) which is configured for the Gigabit transmission mode for the particular port. In addition to the multiple Ethernet interfaces the NAMC-SDH is prepared for optional Fat Pipe support (i.e. XAUI or SRIO) at AMC ports 4-7.

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TECHNISCHE BESCHREIBUNG

proimg1
  • AMC Line Interface between SDH/SONET and TDM
  • AMC module with AMC.2 type 2 E2 interface, mid size or full size form factor
  • XILINX Kintex 7 XC7K325T or KC7K160T
    • SDH interface
    • Time slot interchanger (TSI)
    • iTDM controller
    • Control interface
    • Ethernet interfaces
    • Opt. HDLC controller
  • 2GB DDR3 SDRAM for FPGA
  • Opt. two 72Mbit QDR2+ SRAMs for FPGA
  • TEMUX336 add/drop multiplexer/demultiplexer
    • Four OC-3/STM-1 or two OC-12/STM-4 framers
    • 252 E1 or 336 T1 streams incl. respective clocking information contained in a single STM-1 or STM-4 SDH frame
    • VT1.5/VT-2 or TU-11/TU-12 to VC3/VC4/VC4-4c or STM4/STM4c supported mappings
    • VSF, SLC-96 and ESF T1 framing standards
    • G.704 and G.706 (CRC-4 multiframe) E1 framing standards
  • Four optical 155 Mbit/s OC-3/STM-1 or two 622 Mbit/s OC-12/STM-4 line interfaces in the front panel
  • 4 Gigabit Ethernet interfaces AMC at ports 0, 1, 4 and 8
  • Opt. fat pipe (XAUI or SRIO) at AMC ports 4-7
  • 1000BaseBX iTDM interface
  • Configuration/control via Ethernet
  • Typ. power consumption 3.3V, 12V, 20W
  • 0°C .. +50°C operating temperature range
  • 2 years warranty

Bestellbezeichnungen

NAMC-SDH-00SN

AMC line interface, KC7K325T FPGA

NAMC-SDH-01SN

AMC line interface, KC7K325T FPGA, 72Mbit QDR2+ SRAM

NAMC-SDH-02SN

AMC line interface, KC7K325T FPGA, 2x 72Mbit QDR2+ SRAMs

NAMC-SDH-10SN

AMC line interface, KC7K160T FPGA

NAMC-SDH-11SN

AMC line interface, KC7K160T FPGA, 72Mbit QDR2+ SRAM

NAMC-SDH-12SN

AMC line interface, KC7K160T FPGA, 2x 72Mbit QDR2+ SRAMs

S=0

No transceiver

S=1

STM1 (OC-3)

S=2

STM4 (OC-12)

N=0

No transceiver

N=1

1 STM1 or STM4 transceiver

N=2

2 STM1 or STM4 transceiver

N=3

3 STM1 transceiver

N=4

4 STM1 transceiver

TECHNISCHE DOKUMENTATION

NAMC-SDH user manual